1. Field of the Invention
The present invention relates to a method of making a lightly doped drain (LDD) of a semiconductor device. More particularly, the present invention relates to a method of making an LDD of a low temperature polysilicon thin film transistor (TFT) and a method of making an LDD of a metal oxide semiconductor (MOS) transistor.
2. Description of the Related Art
Distinguishable from conventional amorphous silicon TFT, low temperature polysilicon TFT can have electron mobility of above 200 cm2/V-sec. Consequently, TFT devices can be made in smaller size and with higher aperture ratio so as to enhance the lightness of display panels and decrease power consumption. In addition, part of driving circuits, due to the enhanced electron mobility, the TFT can be formed simultaneously on the glass substrate, so as to improve the property and reliability of the liquid crystal display (LCD) panel and to significantly lower the fabrication costs of the LCD panel. Therefore, the manufacture costs of low temperature polysilicon TFT panels are much lower than the amorphous silicon TFT panels. Moreover, low temperature polysilicon TFT panels, which are characteristically thin in thickness, light in weight and superior in resolution, are especially suitable for making light, portable and power-saving mobile terminal products.
Earlier processes of making low polysilicon TFT panels include using semiconductor apparatus via solid phase crystallization (SPC). Since such processes are performed at a high temperature up to 1000° C., quartz substrates with high melting points must be used. Due to higher costs of quartz substrates compared to glass substrates and size restrictions, panels with quartz substrates can be made in sizes of 2 to 3 inches, and thus only small panels were developed in the past. More recently, with the development of laser technologies, a method of laser crystallization or excimer laser annealing is utilized to transform an amorphous silicon layer to a polysilicon layer. In the process of laser scanning, amorphous silicon is recrystallized to form polysilicon at a temperature lower than 600° C. Thus, glass substrates can be used for making larger TFT LCD panels.
FIGS. 1A to 1D are cross-sectional views illustrating steps of a process of forming an LDD of a conventional low temperature polysilicon TFT.
Referring to FIG. 1A, a patterned polysilicon layer 102 is formed on a substrate 100. In the process of forming the polysilicon layer 102, an amorphous silicon layer (not shown), deposited on the substrate 100, is first transformed to a polysilicon thin film via laser annealing and then defined via a photolithography process and an etching process to form the polysilicon layer 102.
Referring to FIG. 1B, a patterned photoresist layer 104 is formed on the substrate 100, wherein the photoresist layer 104 exposes a area predefined for forming source/drain. Subsequently, an ion implantation process 106 is performed by using the photoresist layer 104 as a mask so as to implant ions into the polysilicon layer 102 not covered by the photoresist layer 104 to form a source 102a and a drain 102b. 
Referring to FIG. 1C, after the photoresist layer 104 is removed, an insulating layer 108 is formed on the substrate 100 to cover the source/drain 102a/102b. A gate 110 is then formed on the insulating layer 108.
Referring to FIG. 1D, a patterned photoresist layer 112 is formed on the insulating layer 108, exposing the gate 110 and a region predefined to form an LDD. An ion implantation process 114 is then performed by using the photoresist layer 112 and the gate 110 as a mask to implant ions into the portion not covered by the photoresist layer 112 and the gate 110 to form an LDD 103. The portion located between the source/drain 102a/102b and the LDD 103 is a channel region 102c of the device.
Therefore, the conventional method of making an LDD of a low temperature polysilicon TFT requires two masking steps and two ion implantation steps, and the process is rather complicated. Especially, since it is not easy to control mask position in two masking steps and may get misaligned, accordingly, it is rather difficult to precisely control the width of the LDD. Any deviation in mask position between two mask steps will lead to discontinuity of the source/drain and the LDD at the interface between the source/drain and the LDD, which will adversely affect the electrical properties of the device.